Tuesday, January 30 | 12:00 p.m.—12:45 p.m.

Keynote Overview: Engineers are facing major challenges within signal integrity, power integrity, and electromagnetic interference — which only seem to increase exponentially. At this rate, where will we be five years from now? Get insights from an all-star panel featuring respected industry leaders as they discuss what’s on the horizon and what the future holds for your company, career, and core industry.

Moderator: Panelists:

Steve Sandler

Managing Director, Picotest

Istvan Novak

Senior Principal Engineer, Oracle

Eric Bogatin

Adjunct Professor, University of Colorado

Alfred Neves

Chief Technologist, Wild River Technology

Kenneth Wyatt

Sr. EMC Engineer, Wyatt Technical Services LLC


Ask us about our custom test fixtures and signal integrity layout services


Custom Channel
Modeling Platform

For development of high-speed systems based on your stack-up.  Includes full HFSS and Simbeor model library to 70 GHz. Deliverables include pristine connector launches and stellar via designs, cross section analysis, and unimpeachable material / loss models.

  • 12 weeks typical completion
  • Launch design 3X better than IEEE PG370 compliance
  • Via and HDI interconnect optimization
  • Material extraction including surface roughness modeling provided
  • Allegro layout (.brd or OBD++)

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32 Gbpsec and 50 GHz
Standard Channel Modeling

Our standard channel modeling platforms are built for enhancing signal integrity workflow confidence to 50 GHz and 32 Gbpsec, so you can benchmark and prove out your solution.

  • EDA Starter Kits (Agilent ADS / Simbeor / Ansys HFSS)
  • Signal integrity training, benchmarking EDA tools
  • Passive/Causal-tested S-parameters provided
  • Allegro layout (.brd or OBD++)

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6-56 Gbpsec
Crosstalk Aggression

The industry’s first tool for Crosstalk generation in 6-32 Gbpsec NRZ and PAM-4 56 Gbpsec systems. Provides crosstalk for low, medium, and high return loss conditions in seconds.

  • IEEE 802.3bj, OIF-CEI 25G LR, COM
  • Mimics backplanes
  • 10µV to 200mV of RX noise
  • Can be used with ISI-28/32 for combining loss and crosstalk
  • Includes Keysight ADS EDA Serial Link kit supporting IBIS-AMI and Single Bit Response optimization
  • Includes S-parameter library for direct EDA serial-link simulations

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Ultra-low Return Loss ISI
(Intersymbol Interference)

For open to closed eye from 6-56 Gbpsec.  using stellar signal integrity Microstrip and Stripline topologies. Pre-silicon EDA capable using supplied S-parameter models.

  • Signal integrity 3X better than IEEE PG370 compliance
  • Very easy to use with complete user’s manual
  • Includes Keysight ADS EDA Serial-Link kit supporting IBIS-AMI and Single Bit Response optimization
  • Includes S-parameter library for direct EDA serial link simulations
  • Pristine launch designs for low return loss
  • Low weave and high signal integrity material for low phase and group delay noise

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