Santa Clara, CA, USA, January 21, 2016: CST – Computer Simulation Technology (CST) and Wild River Technology (WRT) present first results of their cooperation, aimed to demonstrate the correlation of simulation and measurement for high speed digital design at DesignCon 2016, Booth # 627.

New technologies such as DDR 4 and in particular SerDes are pushing electronics to higher speeds.This has increased the need for 3D electromagnetic field simulation in the design process to identify and help avoid signal integrity (SI) and power integrity (PI) issues. To simulate devices accurately, design engineers working in this field require accurate broadband models for interconnects and transmission lines, which need to include effects such as conductor surface roughness and dispersion in dielectric materials. Being able to validate the results against benchmarks increases the engineer’s confidence in the simulation.

Engineers in leading companies in the electronics industry use the CST STUDIO SUITE® software package to analyze Signal and Power integrity. With mature time-domain and frequency-domain solvers, CST® simulation tools have a strong background in applications from classical microwave into the terahertz regime and are well suited to the challenges of high-speed digital design. Wild River Technology meanwhile markets products for high-speed signal integrity engineers who need to characterize high-speed digital systems very accurately. Through the cooperation of CST and WRT, simulations can now be verified against measurements using the CMP-28 Channel Modeling Platform. This is powerful tool for the development of high-speed systems, and includes a range of structures for benchmarking 3D EM simulations and verifying simulation and measurement methods.

“A strong correlation between measurement and simulation is absolutely critical to the successful use of the simulation tools,” said Dr. Klaus Krohne, Market Development Manager EDA, CST. “This cooperation with Wild River Technology means that users can now simulate the behavior of a highspeed channel and then easily check the simulated results against real measured data. This will not only give users more confidence in their results but also help them to avoid some of the common measurement or simulation mistakes that can slow down the development process.”

STANDARD PLATFORMS

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CMP-70

Custom Channel
Modeling Platform



For development of high-speed systems based on your stack-up.  Includes full HFSS and Simbeor model library to 70 GHz. Deliverables include pristine connector launches and stellar via designs, cross section analysis, and unimpeachable material / loss models.

  • 12 weeks typical completion
  • Launch design 3X better than IEEE PG370 compliance
  • Via and HDI interconnect optimization
  • Material extraction including surface roughness modeling provided
  • Allegro layout (.brd or OBD++)

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CMP-28/CMP-32

32 Gbpsec and 50 GHz
Standard Channel Modeling



Our standard channel modeling platforms are built for enhancing signal integrity workflow confidence to 50 GHz and 32 Gbpsec, so you can benchmark and prove out your solution.

  • EDA Starter Kits (Agilent ADS / Simbeor / Ansys HFSS)
  • Signal integrity training, benchmarking EDA tools
  • Passive/Causal-tested S-parameters provided
  • Allegro layout (.brd or OBD++)

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XTALK-32

6-56 Gbpsec
Crosstalk Aggression



The industry’s first tool for Crosstalk generation in 6-32 Gbpsec NRZ and PAM-4 56 Gbpsec systems. Provides crosstalk for low, medium, and high return loss conditions in seconds.

  • IEEE 802.3bj, OIF-CEI 25G LR, COM
  • Mimics backplanes
  • 10µV to 200mV of RX noise
  • Can be used with ISI-28/32 for combining loss and crosstalk
  • Includes Keysight ADS EDA Serial Link kit supporting IBIS-AMI and Single Bit Response optimization
  • Includes S-parameter library for direct EDA serial-link simulations

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ISI-28/ISI-32

Ultra-low Return Loss ISI
(Intersymbol Interference)



For open to closed eye from 6-56 Gbpsec.  using stellar signal integrity Microstrip and Stripline topologies. Pre-silicon EDA capable using supplied S-parameter models.

  • Signal integrity 3X better than IEEE PG370 compliance
  • Very easy to use with complete user’s manual
  • Includes Keysight ADS EDA Serial-Link kit supporting IBIS-AMI and Single Bit Response optimization
  • Includes S-parameter library for direct EDA serial link simulations
  • Pristine launch designs for low return loss
  • Low weave and high signal integrity material for low phase and group delay noise

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