Keysight Webinar

This webcast introduces a forensic channel analysis approach that implements both measurement hardware and EDA tools with contemporary SERDES internal tools (e.g., internal eye scan) for the purpose of optimizing the BER for highly pathological channels (i.e. identifying the major contributors to signal degradation in the link). State-of-the-art pulse response analysis such as this, provides valuable insight into the behavior of the channel and the effective use of CTLE, FFE, and DFE equalization techniques, in order to mitigate crosstalk, attenuation and return loss.

Sponsored by: Keysight Technologies

 

Speakers

Heidi Barnes
Senior Application Engineer
Keysight Technologies

Al Neves
Chief Technologist
Wild River Technology

Jack Carrel
Applications Engineer
Xilinx

Description

Why this webcast is important:
SerDes design engineers often find themselves confronted with channels that prove quite difficult to optimize. “It is all about the margins”.

This webcast introduces a forensic channel analysis approach that implements both measurement hardware and EDA tools with contemporary SERDES internal tools (e.g., internal eye scan) for the purpose of optimizing the BER for highly pathological channels (i.e. identifying the major contributors to signal degradation in the link). State-of-the-art pulse response analysis such as this, provides valuable insight into the behavior of the channel and the effective use of CTLE, FFE, and DFE equalization techniques, in order to mitigate crosstalk, attenuation and return loss.

Specific topics to be covered during this webcast include: optimization, BER, PAM-4, IBIS-AMI, S-parameters, causality, passivity, EQ, DFE, FFE, CTLE, and the latest in pulse response analysis and optimization.

Who should view this webcast:
Engineers and managers working on signal integrity design, characterization, and validation who want insight into the latest tips and techniques for optimizing the physical layer (package, PCBs & interconnects) for 32- to 56- Gbps communication links.

Webinar Registration

Register Here

STANDARD PLATFORMS

Ask us about our custom test fixtures and signal integrity layout services


CMP-70

Custom Channel
Modeling Platform



For development of high-speed systems based on your stack-up.  Includes full HFSS and Simbeor model library to 70 GHz. Deliverables include pristine connector launches and stellar via designs, cross section analysis, and unimpeachable material / loss models.

  • 12 weeks typical completion
  • Launch design 3X better than IEEE PG370 compliance
  • Via and HDI interconnect optimization
  • Material extraction including surface roughness modeling provided
  • Allegro layout (.brd or OBD++)

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CMP-28/CMP-32

32 Gbpsec and 50 GHz
Standard Channel Modeling



Our standard channel modeling platforms are built for enhancing signal integrity workflow confidence to 50 GHz and 32 Gbpsec, so you can benchmark and prove out your solution.

  • EDA Starter Kits (Agilent ADS / Simbeor / Ansys HFSS)
  • Signal integrity training, benchmarking EDA tools
  • Passive/Causal-tested S-parameters provided
  • Allegro layout (.brd or OBD++)

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XTALK-32

6-56 Gbpsec
Crosstalk Aggression



The industry’s first tool for Crosstalk generation in 6-32 Gbpsec NRZ and PAM-4 56 Gbpsec systems. Provides crosstalk for low, medium, and high return loss conditions in seconds.

  • IEEE 802.3bj, OIF-CEI 25G LR, COM
  • Mimics backplanes
  • 10µV to 200mV of RX noise
  • Can be used with ISI-28/32 for combining loss and crosstalk
  • Includes Keysight ADS EDA Serial Link kit supporting IBIS-AMI and Single Bit Response optimization
  • Includes S-parameter library for direct EDA serial-link simulations

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ISI-28/ISI-32

Ultra-low Return Loss ISI
(Intersymbol Interference)



For open to closed eye from 6-56 Gbpsec.  using stellar signal integrity Microstrip and Stripline topologies. Pre-silicon EDA capable using supplied S-parameter models.

  • Signal integrity 3X better than IEEE PG370 compliance
  • Very easy to use with complete user’s manual
  • Includes Keysight ADS EDA Serial-Link kit supporting IBIS-AMI and Single Bit Response optimization
  • Includes S-parameter library for direct EDA serial link simulations
  • Pristine launch designs for low return loss
  • Low weave and high signal integrity material for low phase and group delay noise

> Read More

 

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