Web Tutorial – Analyze and Optimize 32- to 56- Gbps Serial Link Channels

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Date/Time
Date(s) - Jan 26, 2017
10:00 am - 11:00 am

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Why this Webcast is Important

SerDes design engineers often find themselves confronted with channels that prove quite difficult to optimize. “It is all about the margins.”

This webcast introduces a forensic channel analysis approach that implements both measurement hardware and EDA tools with contemporary SERDES internal tools (e.g., internal eye scan) for the purpose of optimizing the BER for highly pathological channels (i.e. identifying the major contributors to signal degradation in the link). State-of-the-art pulse response analysis such as this, provides valuable insight into the behavior of the channel and the effective use of CTLE, FFE, and DFE equalization techniques, in order to mitigate crosstalk, attenuation and return loss.

Specific topics to be covered during this webcast include: optimization, BER, PAM-4, IBIS-AMI, S-parameters, causality, passivity, EQ, DFE, FFE, CTLE, and the latest in pulse response analysis and optimization.

Who Should Attend
Engineers and managers working on signal integrity design, characterization, and validation who want insight into the latest tips and techniques for optimizing the physical layer (package, PCBs & interconnects) for 32- to 56- Gbps communication links.

Register Now for this LIVE Webcast

Presented by:

Heidi Barnes
Senior Application Engineer
Keysight Technologies

Al Neves
Chief Technologist
Wild River Technology

Jack Carrel
Applications Engineer
Xilinx

By registering, you will receive a link to view the webcast on-demand, even if you cannot attend the live event.

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