Technical experts from Samtec, eSilicon and Wild River Technology recently co-presented a webinar around the topic of High-Performance Communications, Delivered.

High-Performance Communc

High-Performance Communications, Delivered

The webinar highlighted technical challenges system designers and engineers face on the way to 56 Gbps/112 Gbps PAM 4 data rates. What are some of those challenges? Here was the agenda:

  • The challenges of high-performance communications, introduction 
    • Dan Nenni, SemiWiki
  • Designing a test board to deliver performance — the Apollo mission model
    • Al Neves, Wild River Technology
  • Delivering the required connectivity
    • Matt Burns, Samtec
  • Putting it all together with eSilicon SerDes
    • Tim Horel, eSilicon

For those unable to attend the webinar live, here is a link to the recording.

Whitepaper: Meeting the demands of PAM4 systems at 56Gbps and beyond

The webinar was a great introduction to the topic. Are other information sources available as well?

Yes. Each webinar registrant can download a new white paper entitled Meeting the demands of PAM4 systems at 56Gbps and beyond. Co-authored by Samtec, eSilicon and Wild River Technology, it details the collaboration and results the partners achieved.

Technology, a winning methodology and the desire to collaborate, all matter.

STANDARD PLATFORMS

Ask us about our custom test fixtures and signal integrity layout services


CMP-70

Custom Channel
Modeling Platform



For development of high-speed systems based on your stack-up.  Includes full HFSS and Simbeor model library to 70 GHz. Deliverables include pristine connector launches and stellar via designs, cross section analysis, and unimpeachable material / loss models.

  • 12 weeks typical completion
  • Launch design 3X better than IEEE PG370 compliance
  • Via and HDI interconnect optimization
  • Material extraction including surface roughness modeling provided
  • Allegro layout (.brd or OBD++)

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CMP-28/CMP-32

32 Gbpsec and 50 GHz
Standard Channel Modeling



Our standard channel modeling platforms are built for enhancing signal integrity workflow confidence to 50 GHz and 32 Gbpsec, so you can benchmark and prove out your solution.

  • EDA Starter Kits (Agilent ADS / Simbeor / Ansys HFSS)
  • Signal integrity training, benchmarking EDA tools
  • Passive/Causal-tested S-parameters provided
  • Allegro layout (.brd or OBD++)

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XTALK-32

6-56 Gbpsec
Crosstalk Aggression



The industry’s first tool for Crosstalk generation in 6-32 Gbpsec NRZ and PAM-4 56 Gbpsec systems. Provides crosstalk for low, medium, and high return loss conditions in seconds.

  • IEEE 802.3bj, OIF-CEI 25G LR, COM
  • Mimics backplanes
  • 10µV to 200mV of RX noise
  • Can be used with ISI-28/32 for combining loss and crosstalk
  • Includes Keysight ADS EDA Serial Link kit supporting IBIS-AMI and Single Bit Response optimization
  • Includes S-parameter library for direct EDA serial-link simulations

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ISI-28/ISI-32

Ultra-low Return Loss ISI
(Intersymbol Interference)



For open to closed eye from 6-56 Gbpsec.  using stellar signal integrity Microstrip and Stripline topologies. Pre-silicon EDA capable using supplied S-parameter models.

  • Signal integrity 3X better than IEEE PG370 compliance
  • Very easy to use with complete user’s manual
  • Includes Keysight ADS EDA Serial-Link kit supporting IBIS-AMI and Single Bit Response optimization
  • Includes S-parameter library for direct EDA serial link simulations
  • Pristine launch designs for low return loss
  • Low weave and high signal integrity material for low phase and group delay noise

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