automatically generated SerDes receive eye diagram

Semiconductor Digest 

| By Kar Yee Tang, eSilicon | February 8, 2020 |

Service providers and hyperscalers — Amazon, Apple, Facebook, Google, Intel and Microsoft — are moving from 100 to 400 gigabit (Gb) Ethernet rates and beyond. Wireline and wireless networks are driving new architectures to support the move from 4G LTE to 5G infrastructure driven by increasing global IP traffic as the world becomes more connected digitally. More...

Channel Modeling Platforms

Ask us about our custom high-speed test fixtures and signal integrity layout services


CMP-70

Custom Channel Modeling
Platform




For development of high-speed systems based on your stack-up. Includes full HFSS and Simbeor model library to 70 GHz. Deliverables include pristine connector launches and stellar via designs, cross section analysis, and unimpeachable material / loss models.

  • Twelve weeks typical completion
  • Launch design 3X better than IEEE PG370 compliance
  • Via and HDI interconnect optimization
  • Material extraction including surface roughness modeling provided
  • Allegro layout (.brd or OBD++)

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CMP-28/CMP-32

32 Gbpsec & 50 GHz
Standard Channel Modeling Platform



Our standard channel modeling platforms are built for enhancing signal integrity workflow confidence to 50 GHz and 32 Gbpsec, so you can benchmark and prove out your solution.

  • EDA Starter Kits (Agilent ADS / Simbeor / Ansys HFSS)
  • Signal integrity training, benchmarking EDA tools
  • Passive/causal-tested S-parameters provided
  • Allegro layout (.brd or OBD++)

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XTALK-32

6-56 Gbpsec
Crosstalk Aggression



The industry’s first tool for crosstalk generation in 6-32 Gbpsec NRZ and PAM-4 56 Gbpsec systems. Provides crosstalk for low, medium, and high return loss conditions in seconds.

  • IEEE 802.3bj, OIF-CEI 25G LR, COM
  • Mimics backplanes
  • 10µV to 200mV of RX noise
  • Can be used with ISI-28/32 for combining loss and crosstalk
  • Includes Keysight ADS EDA serial link kit supporting IBIS-AMI and single-bit response optimization
  • Includes S-parameter library for direct EDA serial-link simulations

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ISI-28/ISI-32

Ultra-Low Return Loss ISI
(Intersymbol Interference)



For open to closed eye from 6-56 Gbpsec. using stellar signal integrity microstrip and atripline topologies. Pre-silicon EDA capable using supplied S-parameter models.

  • Signal integrity 3X better than IEEE PG370 compliance
  • Very easy to use with complete user’s manual
  • Includes Keysight ADS EDA serial-link kit supporting IBIS-AMI and single-bit response optimization
  • Includes S-parameter library for direct EDA serial link simulations
  • Pristine launch designs for low return loss
  • Low weave and high signal integrity material for low phase and group delay noise

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