Simberian News

| September 9, 2020 |
New Simbeor 2021.01 is now available for customers and trials. It provides a huge boost to SI engineer productivity by substantially reducing interconnect model building time. Simbeor 3DML solver is accelerated by 50-100 times on most PCB/packaging problems. Here is a quote from a Simbeor customer who tried it for the first time — “It runs 9-14s/pt instead of 12-18mins/pt!!!!!!! Unbelievable!!!”

It is hard to believe indeed — we had the same impression when we tested our Frontal Accelerator for the first time on Wild River Technology’s CMP-28 and Infinera’s EvR-1 test platforms. EM model building for microstrip launch on CMP-28 took just 7 min instead of 360 min (over 50 times acceleration) and model for microstrip launch on EvR-1 took just 4 min instead of 290 min (over 70 times acceleration). All that with exactly the same accuracy confirmed with the measurements. CMP-28 and EvR-1 Kits with the measured data are available on request — give it a try and compare. More...

Wild River ISI-56 Platform Accelerates SerDes Testing

wild-river-isi-56-platform-accelerates-serdes-testing  Design007 Magazine/PCBDesign007 | By Andy Shaughnessy | February 2, 2021 I recently spoke with Al Neves, founder and CTO of Wild River Technology, about the release of their new ISI-56 loss modeling platform. Al explains why it was so critical that this tool meets the stringent requirements of the IEEE P370 specification (which he helped develop), and why he believes this is currently the best tool for 56G and above SerDes testing and characterization. More...

Characteristic Impedance Where SI/PI Worlds Collide: White Paper

characteristic-impedance-where-si-pi-worlds-collideissue-white-paper LAMSIM Enterprises Inc. | By Bert Simonovich | October 29, 2020 Signal and power integrity (SI/PI) simulations, measurements and analysis usually live in two different worlds, but occasionally these worlds collide. One such collision occurs when we refer to characteristic impedance, Z0. Traditionally the PI world lives in the frequency domain while the SI world lives in the time domain. When designing a power distribution network (PDN) in the PI world, we are mostly interested in engineering a...

Wild River Technology Sets New Standard for 56G SerDes Characterization

wild-river-technology-sets-new-standard-for-56g-serdes-characterizationIntersymbol interference loss modeling platform meets top-tier IEEE P370 standard, expands Wild River Technology portfolio HILLSBORO, Ore. — December 1, 2020 — Wild River Technology, the leading supplier of signal integrity measurement and optimization test fixtures for high-speed channels at data rates of up to 224G, announced today the availability of a new 56G intersymbol interference (ISI) loss modeling platform. Dubbed ISI-56, the platform upgrades the current ISI-32 loss modeling platform...

Simbeor 2021.01 Cuts Model-Building Time From Hours to Minutes

simbeor-2021-01-cuts-model-building-time-from-hours-to-minutes  Design007 Magazine/PCBDesign007 | By Yuriy Shlepnev, Simberian | September 11, 2020 | Simberian has released Simbeor 2021.01, which provides a huge boost of productivity for SI engineers by substantially reducing interconnect model building time. The Simbeor 3DML solver is accelerated by 50-100x on most of PCB/packaging problems. We tested our Frontal Accelerator first time on Wild River Technology’s CMP-28 and Infinera’s EvR-1 test platforms. Electromagnetic model building for microstrip...

New Simbeor 2021.01 is Now Available for Customers and Trials

new-simbeor-2021-01-is-now-available-for-customers-and-trials  Simberian News | September 9, 2020 |New Simbeor 2021.01 is now available for customers and trials. It provides a huge boost to SI engineer productivity by substantially reducing interconnect model building time. Simbeor 3DML solver is accelerated by 50-100 times on most PCB/packaging problems. Here is a quote from a Simbeor customer who tried it for the first time — “It runs 9-14s/pt instead of 12-18mins/pt!!!!!!! Unbelievable!!!” It is hard to believe indeed — we had the same impression when...

Al Neves on Designing for Profitability

al-neves-on-designing-for-profitability Design007 Magazine | By Andy Shaughnessy | March 11, 2020 |If your company is having trouble designing PCBs for profitability, where does the blame fall? Is it management’s fault for having inefficient processes, or is it the fault of the designers and design engineers for not keeping up to date with their training? During DesignCon, I asked Al Neves of Wild River Technology to weigh in on this question. As he explains, you and your manager might both be to blame for inefficiencies in the design...

SerDes Designs: Keeping Pace with a Demanding Network Environment

serdes-designs-keeping-pace-with-a-demanding-network-environment Semiconductor Digest  | By Kar Yee Tang, eSilicon | February 8, 2020 | Service providers and hyperscalers — Amazon, Apple, Facebook, Google, Intel and Microsoft — are moving from 100 to 400 gigabit (Gb) Ethernet rates and beyond. Wireline and wireless networks are driving new architectures to support the move from 4G LTE to 5G infrastructure driven by increasing global IP traffic as the world becomes more connected digitally. More...

WRT partners with eSilicon and Samtec on high-performance communications webinar

wrt-partners-with-esilicon-and-samtec-on-high-performance-communications-webinarTechnical experts from Samtec, eSilicon and Wild River Technology recently co-presented a webinar around the topic of High-Performance Communications, Delivered. High-Performance Communications, Delivered The webinar highlighted technical challenges system designers and engineers face on the way to 56 Gbps/112 Gbps PAM 4 data rates. What are some of those challenges? Here was the agenda: The challenges of high-performance communications, introduction  Dan Nenni, SemiWiki Designing a...
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