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EDI Con 2017 Conference:
“Practical Modeling of High-speed Channels Based on Data Sheet Input”, Bert Simonovich, Lamsim Enterprises Inc.

Article:
“S-parameters: Signal Integrity Analysis in the Blink of an Eye”, Mike Resso, Keysight Technologies; Tim Wang Lee, Keysight Technologies;  Alfred P. Neves, Wild River Technology

DesignCon2017 Paper:
“A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness”, Lambert (Bert) Simonovich, Lamsim Enterprises Inc.
                   DesignCon2017 Best Paper Award Finalist

SI Journal Paper:

“Resonant Test Structures Primer and Signal Integrity Applications”, Al Neves, Tim Wang Lee, Wild River Technology

DesignCon2017 Tutorial:
“32 to 56 Gbps Serial Link Analysis and Optimization Methods for Pathological Channels”, Al Neves, Tim Wang Lee, Wild River Technology; Jack Carrel, Xilinx Inc.; Heidi Barnes, Keysight Technologies

DesignCon2017 Paper:
“BER- and COM-Way of Channel-Compliance Evaluation: What are the Sources of Differences?”, Vladimir Dmitriev-Zdorov, Mentor Graphics; Cristian Filip, Mentor Graphics;
Chuck Ferry, Mentor Graphics; Alfred P. Neves, Wild River Technology
           DesignCon2017 Best Paper Award Winner, Test & Measurement catagory

DesignCon2016 Tutorial Slides:
“A “Material” World, Modeling Dielectrics and Conductors for Interconnects Operating at 10-50 Gbps”, Chudy Nwachukwu, Isola; Yuriy Shlepnev, Simbeor; Scott McMorrow, Teraspeed/Samtec

DesignCon2016 Paper:
“Old School RF Structure Meets Modern Signal Integrity: The Beatty Standard”, Chun-Ting “Tim” Wang Lee, Wild River Technology, University of Colorado at Boulder;  Alfred P. Neves, Wild River Technology
DesignCon2016 Paper:
“BER- and COM-Way of Channel-Compliance Evaluation: What are the Sources of Differences?”, Vladimir Dmitriev-Zdorov, Mentor Graphics; Cristian Filip, Mentor Graphics Chuck Ferry, Mentor Graphics; Alfred P. Neves, Wild River Technology
DesignCon2015 Tutorial:
“Breaking the 32 Gb/s Barrier: PCB Materials, Simulations, and Measurements”, Lee Ritchey, Speeding Edge; Heidi Banes, Keysight Technologies; Chun-Ting “Tim” Wang Lee, Wild River Technology, University of Colorado at Boulder;  Alfred P. Neves, Wild River Technology

The PCB Design Magazine Article:
“Dielectric and Conductor Roughness Models Identification for Successful PCB and Packaging Interconnect Design up to 50 GHz”, Yuriy Shlepnev, Ph.D., Simberian Inc.

DesignCon2014 Presentation:
“The Role of Improved Measurements and Tools in Assessing Simulation-Measurement Correspondence for 32 Gbps”, Bob Buxton, Anritsu Company; Alfred P. Neves, Wild River Technology

DesignCon2014 Paper:
“Managing S-parameter Data for 10 to 32 Gb/s Time-Domain Simulations”, James Bell, Wild River Technology; Bob Buxton, Anritsu Company; Jon Martens, Anritsu Company; Alfred P. Neves, Wild River Technology
DesignCon2014 Paper:
“Cracking the Code of 32 Gbpsec Differential Vias with Advanced Time Domain Methods”, Josiah Bartlett, Tektronix; James Bell, Wild River Technology; Tom Dagostino, Teraspeed Consulting Group; Al Neves, Wild River Technology; Michael Steinberger, SiSoft
DesignCon2013 Tutorial:
“Methods of Improving 3D EM Model Development and Associated Time/Frequency Domain Measurements”, James Bell, Wild River Technology; Al Neves, Wild River Technology ;Bob Buxton, Anritsu Company; Jon Martens, Anritsu Company; Josiah Bartlett, Tektronix

DesignCon2012 Paper:
“Robust Method for Addressing 12 Gbps Interoperability for High-Loss and Crosstalk-Aggressed Channels”, James Bell, Wild River Technology; Alan Blankman, LeCroy Corporation ; Eric Bogatin, Bogatin Enterprises; Alfred Neves, Wild River Technology; George Noh, Vitesse Semiconductor; Martin Spadaro, Vitesse Semiconductor
DesignCon2011 Paper:
“Developing Unified Methods of 3D Electromagnetic Extraction, System Level Channel Modeling, and Robust Jitter Decomposition in Crosstalk Stressed 10 Gbpsec Serial Data Systems”, James Bell, Wild River Technology; Scott McMorrow, Teraspeed Consulting Group; Martin Miller, LeCroy Corp; Alfred Neves, Wild River Technology

DesignCon2010 Paper:
“Full-wave time domain modeling of interconnects”, Martin Schauer, Computer Simulation Technology; Alfred Neves, Teraspeed Consulting Group,Tom Dagostino, Teraspeed Consulting Group; Scott McMorrow, Teraspeed Consulting Group

DesignCon2010 Paper:
“Practical identification of dispersive dielectric models with generalized modal S-parameters for analysis of interconnects in 6-100 Gb/s applications”, Yuriy Shlepnev, Simberian Inc.; Alfred Neves, Teraspeed Consulting Group; Tom Dagostino, Teraspeed Consulting Group; Scott McMorrow, Teraspeed Consulting Group

2009 Presentation:
“Calibration and De-Embedding Techniques In the Frequency Domain”, Al Neves, Teraspeed Consulting Group; Tom Dagostino, Teraspeed Consulting Group

DesignCon2009 Paper:
“Measurement-Assisted Electromagnetic Extraction of Interconnect Parameters on Low-Cost FR-4 Boards for 6-20 Gb/sec Applications”, Yuriy Shlepnev, Simberian Inc.; Al Neves, Teraspeed Consulting Group; Tom Dagostino, Teraspeed Consulting Group; Scott McMorrow, Teraspeed Consulting Group
DesignCon2004 Paper:
“Identifying Sources of Jitter”, Johnnie Hancock, Agilent Technologies

DesignCon2004 Paper:
“A Hybrid Measurement and Electromagnetic Field Solver Approach for the Design of High-Performance Interconnects: An Investigation of Traces and SMA Transitions”Al Neves, Teraspeed Consulting Group; Scott McMorrow, Teraspeed Consulting Group