This work presents a novel approach of PCB vias design and optimization for 112 and 224 Gb applications. As data rates go up, vias are becoming increasingly important for signal integrity yet increasingly challenging in successful real-life implementation due to the necessity of tighter control over via’s properties such as signal reflection, dissipation, and crosstalk at higher frequencies. Vias design is often becoming the limiting factor for the ultra-high-speed channel performance. To make matters worse vias electrical performance at high frequencies is often dominated by PCBs and Package manufacturing variations. We explore the physics of vias – conditions and metrics for localization within single-mode bandwidth up to 120 GHz. A novel approach is introduced to design for robustness against manufacturing variation, stackup adjustments due to copper density or multi-sourcing support. We demonstrate a practical design methodology prioritizing low sensitivity to these factors while meeting the low reflection criteria. The paper demonstrates some insights into the practical discrepancies between theoretical designs and manufactured vias, bridging the theory with realities.
