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Achieving high levels of accuracy between predicted and actual performance is a critical goal for any team doing advanced chip design. Getting what you expect from manufacturing can cut design time, improve cost margins, decrease time to market and generally improve overall success for the project. Achieving this goal is not easy. Many design [...]

Serdes Designer, Characterization folks, I am seeing commercial ISI platforms (the latest one is on sale) that have rather mediocre return-loss (SDD11) in the 1X Nyquist region for 112G PAM4.  Our ISI-112 has almost -30dB of return-loss through 53GHz, with 10dB margin at 67GHz!  This is by far the industry’s best performance. Return loss reflect energy, which [...]

Join Eric Bogatin, SIJ Technical Editor in episode 4 as he chats with Al Neves, President and Founder of Wild River Technology. Al is also a member of the SIJ Editorial Advisory Board. Hear Al's experiences developing the methodologies to create 1-spin extreme signal integrity boards operating at 56 Gbps and 112 Gbps PAM4 and [...]

Emerging 100 Gigabit Ethernet and 400 Gigabit Ethernet requirements for communication networks have put increasing demands on Internet infrastructure. New methods of design, validation, and troubleshooting to optimize high speed digital channels are being employed in the R&D laboratory. This article discusses new concepts for serial link design and analysis as applied to physical layer [...]

In this Signal Integrity Journal article, Vladimir Dmitriev-Zdorov, Cristian Filip, Chuck Ferry, and Alfred P. Neves, CTO of Wild River Technology, analyze the computational procedure specified for Channel Operation Margin (COM) and compare it to traditional statistical eye/BER analysis. There are a number of differences between the two approaches, ranging from how they perform channel [...]