High-Speed Signal Integrity Webinars
Explore the collection of webinars below covering high-speed serial link analysis, EDA simulation techniques, and signal integrity optimization. Gain insights into channel analysis, fixture de-embedding, and advanced modeling strategies to improve simulation accuracy and measurement precision.
The discussion focuses on PAM4 (pulse amplitude modulation) systems operating at 56 Gigabits per second and beyond. PAM4 is a modulation technique whereby four distinct pulse amplitudes are used to convey the information.
This webcast introduces a forensic channel analysis approach that implements both measurement hardware and EDA tools with contemporary SerDes internal tools (e.g., internal eye scan) for the purpose of optimizing the BER for highly pathological channels (i.e. identifying the major contributors to signal degradation in the link). State-of-the-art pulse response analysis such as this, provides valuable insight into the behavior of the channel and the effective use of CTLE, FFE, and DFE equalization techniques, in order to mitigate crosstalk, attenuation and return loss.
Specific topics to be covered include: optimization, BER, PAM-4, IBIS-AMI, S-parameters, causality, passivity, EQ, DFE, FFE, CTLE, and the latest in pulse response analysis and optimization.
This video provides a quick overview of how fixture de-embedding from measurements, or embedding into simulations is a critical step for matching simulations to measurements for physical layer Tx to Rx channels. Multigigabit channels that include multi-layer laminate or printed circuit board structures require a fixture to go from the coaxial connections of the measuring instrument to the planar transmission line structures on a PCB. This fixture is not calibrated out by the coaxial calibration of the instrument and is often neglected in the simulation.
This seminar will help you achieve this level of modeling measurement using Simbeor as demonstrated using Wild River Technology’s CMP-28 Advanced Channel Modeling Platform in a systematized and high-confidence approach
Step 1: Measure S-parameters and validate quality Step 2: Import and adjust stack-up and board geometry into EDA tool Step 3: Identify broadband dielectric and conductor roughness models Step 4: Simulate all structures on the validation board without further adjustments and compare magnitude and phase of S-parameters, TDR/TDT and eye diagrams
