• Extreme Signal Integrity Design to 110GHz
  • ATE Device Interface Board Design
  • SERDES characterization
  • Backplane design
  • Connector test fixtures
  • RF Optimizations

“I brought Al’s team in to design a high-speed SERDES IP customer evaluation platform board design. It was intended to support 56G and 112G PAM4 silicon. The test platform worked great to 67 GHz. We successfully used that board for numerous customer evaluations and trade shows. The lab in Italy later used it to validate their 112G SERDES design.”

Tim Horel, eSilicon