ICYMI: High-Performance Communications, Delivered

Samtec Blog

By Matt Burns | July 24, 2019 
ICYMI. Doesn’t that immediately induce fear of missing out? Oh wait, that’s another acronym. FOMO. Yikes. In any case, technical experts from Samtec, eSilicon and Wild River Technology recently co-presented a webinar around the topic of High-Performance Communications, Delivered. The webinar highlighted technical challenges system designers and engineers face on the way to 56 Gbps/112 Gbps PAM 4 data rates. What are some of those challenges? More...

July 2019 Connector Industry News

Connector Supplier

By Christine Stieglitz | July 9, 2019
Samtec, eSilicon, and Wild River Technology have co-developed a next-generation test platform that addresses common challenges OEMS face when developing high-performance communications solutions and are promoting it via webinar on Thursday, July 11. The “High-Performance Communications, Delivered” webinar will focus on high-performance communications at 56Gb/s PAM4 and beyond and will also provide an introduction to the challenges of high-performance communications. More...

Samtec Partners with eSilicon and Wild River Technology on High-Performance Communications Webinar

Wild River, eSilicon, and Samtec Team up for 112-Gbps Test Vehicle

Design007 Magazine

By Andy Shaughnessy | June 6, 2019
During DesignCon, I sat down for an interview with Tim Horel from eSilicon, Al Neves of Wild River Technology, and Matt Burns from Samtec. They’ve recently teamed up to create a 112-Gbps test vehicle that may be the first of its kind of test fixture.

Al Neves: Well, there’s a science-fiction comment that’s really appropriate: “In space, everything can kill you.” And when you’re doing work even at 56 Gbps, the requirements of the PAM4 technology for test fixturing is formidable; everything needs to be top-tier SI metrics. There’s a new emerging standard—IEEE P370—that helps with our guidance of that, and we use it along with some simulations as a guide to establish metrics for doing the 3D EM optimization. The 3D EM optimization was the floor plan—the SI of the platform. Most importantly, the crux issue was the high-density interconnect, which was the Bulls Eye connector from Samtec going into the board.

For the electromagnetic simulation, we had two internal teams, and we also used an external Samtec team. Our experience using external teams from connector companies was universally very negative. They’re not usually up to the requirements of the advanced SI that you need for PAM4. However, the Samtec team did a fabulous job. In fact, we used three independent teams—two internal teams using two different tools, and then a Samtec team—and we overlaid all of those. Samtec’s results and the Wild River team’s overlaid very closely and the synergy between the teams was really brilliant. More...

112G Digs in at DesignCon 2019

EEWeb

By Martin Rowe | February 12, 2019
112G serial links have moved out of the lab and onto the exhibit floor. 56G ramps up while 28G goes mainstream.

Last year at DesignCon 2018, we witnessed high-speed digital designs that moved past 56 Gbits/s (56G) and onto 112 Gbits/s (112G). This year, DesignCon 2019 brought numerous demonstrations of 112G as the connectors and cables caught up with the silicon. While still appearing in technical papers and panels, 112G has certainly moved into the exhibit hall. Meanwhile, 56G has matured and is now a complete ecosystem.

When it comes to signal integrity and high-speed signals, transmission lengths certainly matter, especially with electrical signals over copper connections. Yes, optical transmission is an option, but nobody wants to pay for it. More…

DesignCon 2019 — Open Your Eyes

Signal Integrity Journal

By Patrick Hindle | February 11, 2019
eSilicon was in the Samtec booth presenting their collaboration with Wild River Technology and Samtec to develop an advanced test system that addresses the incredible signal integrity demands of 56/112G PAM4 operation. The test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance.

High-speed design: It takes a village to succeed
eSilicon, Wild River Technology, and Samtec combined forces to develop a 56-Gbits/s test board

Electronic Products

By Martin Rowe | February 82019
You’ve probably heard the phrase “It takes a village to raise a child.” The same can be said for high-speed digital design. That’s the lesson that engineers at eSilicon, Wild River Technologies, and Samtec learned when eSilicon needed a board to test its latest 56-/112-Gbits/s PAM4 SerDes for use in IEEE 802.3bs (200-/400-Gbits/s Ethernet) and several Optical Internetworking Forum (OIF) implementations.

To find out how the three companies worked on the problem, I met on Jan. 30 with representatives of the three companies at DesignCon 2019 in Santa Clara, California.

“We needed a way to evaluate our chip,” said eSilicon’s director of field applications, Tim Horel. The board not only lets eSilicon engineers do that, it also serves as a reference design. The goal was to design a board that could pass data at a bit-error ratio (BER) of 10E-11 over 5m of copper cable without the need for forward-error correction (FEC). The board, which was on display at DesignCon 2019, can maintain that BER over 7m of copper, according to eSilicon’s VP of marketing, Mike Gianfanga. More...

Week In Review: Design, Low Power
Formal connectivity checking; EM interference in PCBs; 7nm GDDR6 PHY; advanced 56G/112G PAM4 test board

Semiconductor Engineering

By Jesse Allen | February 1, 2019
eSilicon teamed up with Wild River Technology on an operation using the upcoming IEEE P370 standard. The design employed a channel-modeling platform to improve de-embedding quality out past 70GHz, establishing clear targets of equalization and creating an advanced reference design suited for immediate 3D electromagnetic design. The core of the design was Samtec’s Bulls Eye Test Point System; tools were also used from Keysight, ANSYS, and Simberian. The next phase is to design and build a test socket suited for 70GHz. More...

High-Speed Communication Takes A Village

Semiconductor Engineering

By Mike Gianfagna | January 31, 2019
Forget the notion of a simple test fixture. This stuff is a lot more complicated than that. It starts with a specification — the complex set of capabilities required to “hit the target.” In this case, it’s the emerging IEEE P370 standard. According to the official website: “The standard is applicable to: PCB and related interconnects (including package, connector, cable, etc.) used in high-speed digital applications, operating with signals at frequencies up to 50 GHz.” To validate the performance of our 56G SerDes, we set out to build a test board that conformed to this specification. More...

eSilicon and Wild River Technology Announce Advanced SerDes Test System
System addresses the demands of 56/112G PAM4 operation using upcoming IEEE P370 standard

eSilicon Press Release

January 30, 2019
eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, in collaboration with Wild River Technology, announced today at DesignCon 2019 the availability of an advanced test system that addresses the incredible signal integrity demands of 56/112G PAM4 operation.

High baud-rate PAM4 test/characterization systems are challenging to design due to the high demands for superior signal integrity and signal-to-noise ratio (SNR). The test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance. Keysight’s Advanced Design System was used to explore power spectral density, examining how much bandwidth is needed for effective testing and what specific metrics of IEEE P370 are most important, such as return loss, equivalent return loss, time-domain reflectometry (TDR) and impedance analysis. eSilicon’s 56G PAM4 & NRZ DSP-based 7nm SerDes was used to drive the communication channels. More...

Moving From 28 Gbps NRZ to 56 Gbps PAM-4: Is it a Free Lunch?

Design007 Magazine, Page 64

By Yuriy Shlepnev, Simberian | August 2018
The usual way of signaling through PCB interconnects is a two-level pulse, an encoding of 1s and 0s or bits, named NRZ (non-returnto-zero) or PAM-2 line code type. Increasing the data rate with the NRZ code type presents some obstacles. For a 28 Gbps NRZ signal, the bit time is about 35.7 ps with the main spectral lobe below 28 GHz. For a 56 Gbps NRZ signal, the bit time is about 17.86 ps, with the main spectral lobe below 56 GHz. One can feel the problem already: Getting PCB interconnect analysis and measurements up to 56 GHz and beyond is very challenging, to say the least. In addition, the expected attenuation (dielectric, conductor and roughness losses) would also be an obstacle for 56 GHz NRZ. To reduce the bandwidth of the signal, pulse amplitude modulation with four levels (PAM-4) is being used more frequently on production boards. More...

Analyze post-equalization ISI with pulse response

EDN

By Ransom Stephens | March 7, 2018
Any signal-integrity engineer will tell you that analyzing closed eye diagrams has never been easy. A transmission channel's frequency response (or lack of bandwidth) causes inter-symbol interference (ISI), the primary eye-closing culprit. While I've written about closed eye analysis techniques before, this time we'll measure the ISI left over after equalization, the so-called residual ISI. In the process, we'll see the simple guts of decision feedback equalization (DFE). More...

SI, PI, and EMI Have a Simpler, More Integrated Future

Design News

By Chris Wiltz | January 31, 2018
A panel of experts at DesignCon 2018 said that signal integrity, power integrity, and electromagnetic integrity aren't going to be separate disciplines any longer. But how can engineers address the new challenges ahead?

If you want to think about where signal integrity (SI), power integrity (PI), and electromagnetic integrity (EMI) are going in the next five years, the first thing you need to do is stop thinking about them separately.

“SI, PI, and EMI won't be three technologies anymore. We're going to have to deal with them all simultaneously,” Steve Sandler, Managing Director at Picotest, told the DesignCon 2018 audience at a keynote panel, “SI/PI & EMI Challenges: Looking Ahead Through 2023.”

Sandler and a group of panelists that included Istvan Novak, Senior Principal Engineer at Oracle; Eric Bogatin, an Adjunct Professor at University of Colorado's Department of Electrical, Computer, and Energy Engineering; Alfred Neves, Chief Technologist at Wild River Technology; and Kenneth Wyatt, Senior EMC Engineer at Wyatt Technical Services, all concluded that the proliferation of Internet of Things (IoT) technologies, coupled with new forms of computing and emerging technologies like autonomous vehicles, is going to conflate signal, power, and electromagnetism concerns in ways that will present brand new challenges for engineers and force experts in one area to gain experience in the others, as well. More...

10 Must-See Moments at DesignCon 2018

Connector Supplier

January 15, 2018
This year, DesignCon promises a full array of events, including technical sessions, panels, training boot camps, and hundreds of exhibits featuring the latest connector technology.

DesignCon is one of the premier conferences and exhibitions for the high-speed communications and semiconductor communities. Held each year in Santa Clara, California, this jam-packed three-day event includes continuing education opportunities, an expo highlighting the latest technologies, and networking opportunities across industries. There’s so much — you just can’t do it all. But, plan carefully and you can make the most of this experience. (DesignCon’s handy schedule builder is a great planning tool.) Here are 10 must-see moments you’ll want to add to your itinerary. More...

Tim’s Blackboard #8: Eye-opening Experience with CTLE

Keysight Technologies Blog

By Tim Wang Lee | Dec 5, 2017
Welcome to Tim’s Blackboard! This is the place to find discussions on interesting topics related to signal integrity and power integrity. This week on Tim’s Blackboard is “Eye-opening Experience with CTLE,” where we study one of the equalization techniques. This post has an associated ADS workspace. Today, we will take a close look at continuous-time linear equalization (CTLE) and how it opens closed eyes for us. More…

S-Parameters: Signal Integrity Analysis in the Blink of an Eye

Signal Integrity Journal

By Alfred P. Neves, Mike Resso, and Chun-Ting Wang Lee | May 30, 2017
Emerging 100 Gigabit Ethernet and 400 Gigabit Ethernet requirements for communication networks have put increasing demands on Internet infrastructure. New methods of design, validation, and troubleshooting to optimize high speed digital channels are being employed in the R&D laboratory. This article discusses new concepts for serial link design and analysis as applied to physical layer test and measurement techniques. Novel test fixtures and signal integrity software tools will be discussed in real world applications in the form of design case studies.

BER- and COM-Way of Channel-Compliance Evaluation: What are the Sources of Differences?

Signal Integrity Journal

Vladimir Dmitriev-Zdorov, Cristian Filip, Chuck Ferry, and Alfred P. Neves | March 23, 2017
We analyze the computational procedure specified for channel operation margin (COM) and compare it to traditional statistical eye/BER analysis. There are a number of differences between the two approaches, ranging from how they perform channel characterization, to how they consider Tx and Rx noise and apply termination, to the differences between numerical procedures employed to convert given jitter and crosstalk responses into the vertical distribution characterizing eye diagrams and BER. We show that depending on the channel COM may potentially overestimate the effect of crosstalk and, depending on a number of factors, over- or underestimate the effect of transmit jitter, especially when the channel operates at the rate limits. We propose a modification to the COM procedure that eliminates these problems without considerable work increase. More...

Obsessing Over Conductor Surface Roughness: What’s the Effect on Dk?

The PCB Design Magazine, Page 44

By Bert Simonovich, Lamsim Enterprises | March 2017
You know you have an obsession when you are flying six miles over Colorado and you look out the window at the beautiful scenery, and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well, call me obsessed, because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, California.

For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year at DesignCon, I presented a paper titled “A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness.” Everyone involved in the design and manufacture of PCBs knows that one of the most important properties of the dielectric material is the relative permittivity, commonly referred to as dielectric constant (Dk). But in reality, Dk is not constant at all. It varies over frequency as you will see later. More...

32 to 56 Gbps Serial Link Analysis and Optimization Methods for Pathological Channels

DesignCon 2017

By Al Neves, Tim Wang Lee (Wild River Technology); Jack Carrel, Hong-Ahn (Xilinx, Inc.); Heidi Barnes, Mike Resso (Keysight Technologies) | February 10, 2017
For many SerDes applications, when there is a channel that is proving difficult to achieve the required BER performance, the question of where and what to apply to the effort must be answered. The key focus of this tutorial is to unite a concerted channel analysis approach implementing both measurement hardware and EDA tools with contemporary SERDES internal tools (internal eye scan) for the purpose of optimizing BER for highly pathological channels (crosstalk, loss, return loss degradation, etc.). More...

 

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